- 张靖恺;李崇仁;田超;余菲;
This paper presents an on-chip measurement circuit to measure multi-giga bit cycle-to-cycle jitter based on the vernier oscillator (VO), which is inherited from the famous vernier delay line. The calibration method is also given. The circuit adopts a differential digital controlled delay element, which makes the circuit flexible in adjusting the measurement resolution, and a highly sensitive phase capturer, which makes the circuit able to measure jitters in pico-second range. The parallel structure makes it possible to measure consecutive cycle-to-cycle jitters. The performance of the circuit was verified via simulation with SMIC 0.18 μm process. During simulation under the clock with the period of 750 ps, the error between the measured RMS jitter and the theoretical RMS jitter was just 2.79 ps. Monte Carlo analysis was also conducted. With more advanced technology, the circuit can work better. This new structure can be implemented in chips as a built-in self-test IP core for testing jitter of PLL or other clocks.
2007年S1期 1-7页 [查看摘要][在线阅读][下载 551K] [下载次数：62 ] |[网刊下载次数：0 ] |[引用频次：1 ] |[阅读次数：0 ] - 杨金民;张大方;李建勋;程京;
Wide-area systems are becoming a popular infrastructure for long-running applications. Rollback- recovery, as a common technology for fault tolerance and load balance, must meet the challenges of scalability and inherent variability in such applications. Most of the rollback-recovery protocols, however, are poor in scalability. Although pessimistic message logging protocols have no such problem, their fault-free overhead sometimes is prohibitive. Aiming at good scalability and acceptable overhead, this paper introduces the concept of pessimism grain and presents a coarse-grained pessimistic message-logging scheme. The paper also evaluates the impact of pessimism grain on the performance of the recovery scheme. Experimental results show that pessimism grain is one of the key configuration parameters to reach a desired performance level. In practice, the proper pessimism grain should be selected based on the characteristics of the applications.
2007年S1期 8-13页 [查看摘要][在线阅读][下载 435K] [下载次数：43 ] |[网刊下载次数：0 ] |[引用频次：0 ] |[阅读次数：0 ] - 高传平;段洣毅;谈利群;宫云战;
Out-of-bounds array access(OOB) is one of the fault models commonly employed in the objectoriented programming language. At present, the technology of code insertion and optimization is widely used in the world to detect and fix this kind of fault. Although this method can examine some of the faults in OOB programs, it cannot test programs thoroughly, neither to find the faults correctly. The way of code insertion makes the test procedures so inefficient that the test becomes costly and time-consuming. This paper, uses a kind of special static test technology to realize the fault detection in OOB programs. We first establish the fault models in OOB program, and then develop an automatic test tool to detect the faults. Some experiments have exercised and the results show that the method proposed in the paper is efficient and feasible in practical applications.
2007年S1期 14-19页 [查看摘要][在线阅读][下载 432K] [下载次数：52 ] |[网刊下载次数：0 ] |[引用频次：4 ] |[阅读次数：0 ] - 文科;胡瑜;李晓维;
Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental results on ISCAS'89 benchmarks show that 100% fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.
2007年S1期 20-25页 [查看摘要][在线阅读][下载 467K] [下载次数：30 ] |[网刊下载次数：0 ] |[引用频次：10 ] |[阅读次数：0 ] - 胡梅;王红;胡庚;杨士元;
Fault diagnosis is very important for development and maintenance of safe and reliable electronic circuits and systems. This paper describes an approach of soft fault diagnosis for analog circuits based on slope fault feature and back propagation neural networks (BPNN). The reported approach uses the voltage relation function between two nodes as fault features; and for linear analog circuits, the voltage relation function is a linear function, thus the slope is invariant as fault feature. Therefore, a unified fault feature for both hard fault (open or short fault) and soft fault (parametric fault) is extracted. Unlike other NN-based diagnosis methods which utilize node voltages or frequency response as fault features, the reported BPNN is trained by the extracted feature vectors, the slope features are calculated by just simulating once for each component, and the trained BPNN can achieve all the soft faults diagnosis of the component. Experiments show that our approach is promising.
2007年S1期 26-31页 [查看摘要][在线阅读][下载 368K] [下载次数：189 ] |[网刊下载次数：0 ] |[引用频次：31 ] |[阅读次数：0 ] - 王真;江建慧;杨光;
The development of VLSI technology results in the dramatically improvement of the performance of integrated circuits. However, it brings more challenges to the aspect of reliability. Integrated circuits become more susceptible to soft errors. Therefore, it is imperative to study the reliability of circuits under the soft error. This paper implements three probabilistic methods (two pass, error propagation probability, and probabilistic transfer matrix) for estimating gate-level circuit reliability on PC. The functions and performance of these methods are compared by experiments using ISCAS85 and 74-series circuits.
2007年S1期 32-38页 [查看摘要][在线阅读][下载 431K] [下载次数：55 ] |[网刊下载次数：0 ] |[引用频次：3 ] |[阅读次数：0 ] - 那宝玉;张毓森;刘丽丽;刘鹏;
This paper presents a novel method, called TSHOVER, for tolerating up to triple disk failures in RAID/DRAID architectures or others reliable storage systems. TSHOVER is two-dimensional code, which employs horizontal code and vertical code at the same time with simple exclusive-OR (XOR) computations. This paper shows the new step ascending concepts used in encoding, and it has the capability of realizing fault tolerance. TSHOVER has better data recovery ability to those disk network storage systems with relatively more dynamic changes in the number of disks. Compared with RS and STAR code, TSHOVER has better encoding performance. When updating a data strip, only 6 XOR operations are needed. Both experimental results and theoretical analyses show that TSHOVER has better performance and higher efficiency than other algorithms.
2007年S1期 39-44页 [查看摘要][在线阅读][下载 500K] [下载次数：38 ] |[网刊下载次数：0 ] |[引用频次：3 ] |[阅读次数：0 ] - 王乘;蒋从锋;刘小虎;
The uncertainties of grid sites security are main hurdle to make the job scheduling secure, reliable and fault-tolerant. Most existing scheduling algorithms use fixed-number job replications to provide fault tolerant ability and high scheduling success rate, which consume excessive resources or can not provide sufficient fault tolerant functions when grid security conditions change. In this paper a fuzzy-logic-based self-adaptive replication scheduling (FSARS) algorithm is proposed to handle the fuzziness or uncertainties of job replication number which is highly related to trust factors behind grid sites and user jobs. Remote sensing-based soil moisture extraction (RSBSME) workload experiments in real grid environment are performed to evaluate the proposed approach and the results show that high scheduling success rate of up to 95% and less grid resource utilization can be achieved through FSARS. Extensive experiments show that FSARS scales well when user jobs and grid sites increase.
2007年S1期 45-50页 [查看摘要][在线阅读][下载 403K] [下载次数：57 ] |[网刊下载次数：0 ] |[引用频次：0 ] |[阅读次数：0 ] - 裴颂文;吴百锋;朱琨;余强;
Software automated testing is one of the critical research subjects in the field of computer application. In this paper, a novel design of architecture called automated testing system (ATS) is proposed. Based on techniques relating to J2EE including MVC design pattern, Struts framework, etc, ATS can support any black-box testing business theoretically with relevant APIs programmed using Tcl script language beforehand. Moreover, as the core of ATS is built in Java, it can work in different environments without being recomplied. The efficiency of the new system is validated by plenty of applications in communication industry and the results also show the effectiveness and flexibility of the approach.
2007年S1期 51-56页 [查看摘要][在线阅读][下载 490K] [下载次数：198 ] |[网刊下载次数：0 ] |[引用频次：45 ] |[阅读次数：0 ] - 孙强;周涛;李海军;
In the course of high-level synthesis of integrate circuit, the hard-to-test structure caused by irrational schedule and allocation reduces the testability of circuit. In order to improve the circuit testability, this paper proposes a weighted compatibility graph (WCG), which provides a weighted formula of compatibility graph based on register allocation for testability and uses improved weighted compatibility clique partition algorithm to deal with this WCG. As a result, four rules for testability are considered simultaneously in the course of register allocation so that the objective of improving the design of testability is acquired. Tested by many experimental results of benchmarks and compared with many other models, the register allocation algorithm proposed in this paper has greatly improved the circuit testability with little overhead on the final circuit area.
2007年S1期 57-60页 [查看摘要][在线阅读][下载 318K] [下载次数：41 ] |[网刊下载次数：0 ] |[引用频次：4 ] |[阅读次数：0 ] - 牛道恒;王红;杨士元;成本茂;靳洋;
Balanced wrapper scan chains are desirable for system-on-chip (SoC) testing because they minimize the time required to transport the test data. A new heuristic algorithm is proposed based on mean- value approximation and implement fast re-optimization as a subsequence of an earlier best-fit-decrease (BFD) method. The mean length of each scan chain was introduced as an approximation target to balance different scan chains and hence saved testing time. Experimental results present both for assumed arbitrary cores and cores from ITC'02 benchmark and show the effectiveness of the algorithm. The proposed algorithm can provide more balanced wrapper design efficiently for the test scheduling stage.
2007年S1期 61-66页 [查看摘要][在线阅读][下载 378K] [下载次数：62 ] |[网刊下载次数：0 ] |[引用频次：24 ] |[阅读次数：0 ] - 骆祖莹;
With technology scaling into nanometer regime, rampant process variations impact visible influences on leakage power estimation of very large scale integrations (VLSIs). In order to deal with the case of large inter- and intra-die variations, we induce a novel theory prototype of the statistical leakage power analysis (SLPA) for function blocks. Because inter-die variations can be pinned down into a small range but the number of gates in function blocks is large(>1000), we continue to simplify the prototype. At last, we induce the efficient methodology of SLPA. The method can save much running time for SLPA in the low power design since it is of the local-updating advantage. A large number of experimental data show that the method only takes feasible running time (0.32 s) to obtain accurate results (3 σ-error <0.5% on maximum) as function block circuits simultaneous suffer from 7.5%(3 σ/mean) inter-die and 7.5% intra-die length variations, which demonstrates that our method is suitable for statistical leakage power analysis of VLSIs under rampant process variations.
2007年S1期 67-72页 [查看摘要][在线阅读][下载 420K] [下载次数：42 ] |[网刊下载次数：0 ] |[引用频次：1 ] |[阅读次数：0 ] - 李明;徐拾义;万发雨;辜建伟;彭明明;姜竞赛;
A non-intrusive design of self-checking finite state machines (FSMs) in VLSI circuits was investigated using convolutional codes. We propose a novel scheme which cannot only detect but also correct errors occurred in FSM states. The error state will be corrected and sent back to the FSM, so that the concurrent error in the current state is detected and corrected immediately. Moreover, we realize the IP core of the self-checking module by SMIC 0.25-μm CMOS technology and also simulate its function in FPGA.
2007年S1期 73-77页 [查看摘要][在线阅读][下载 493K] [下载次数：62 ] |[网刊下载次数：0 ] |[引用频次：2 ] |[阅读次数：0 ] - 胡庚;王红;胡梅;杨士元;
A test strategy for analog filters was proposed. The output voltage and supply current of the circuit were monitored when using the oscillation test technique. The frequency, average value, maximum value and amplitude of both output voltage and supply current were taken as test parameters. Tolerance bands of test parameters were analyzed. Fault detectabilities of test parameters were compared and combined, and optimal parameter sets were derived. Experimental results show that both the output voltage and supply current give significant contribution to fault detection. Considering catastrophic, single and double parametric faults, the fault coverage in testing the benchmark circuit can be raised from 90.6% for traditional voltageonly oscillation test strategy to 97.2% by monitoring both output voltage and current parameters.
2007年S1期 78-82页 [查看摘要][在线阅读][下载 363K] [下载次数：54 ] |[网刊下载次数：0 ] |[引用频次：0 ] |[阅读次数：0 ] - 王飞;胡瑜;李晓维;
Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the subsequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we propose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue. Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness of our design.
2007年S1期 83-88页 [查看摘要][在线阅读][下载 362K] [下载次数：46 ] |[网刊下载次数：0 ] |[引用频次：1 ] |[阅读次数：0 ] - 林腾;冯建华;王阳元;
This paper presents an improved test data compression scheme based on a combination of test data compatibility and dictionary for multi-scan designs to reduce test data volume and thus test cost. The proposed method includes two steps. First a drive bit matrix with less columns is generated by the compatibilities between the columns of the initial scan bit matrix, also the inverse compatibilities and the logic dependencies between the columns of mid bit matrixes. Secondly a dictionary bit matrix with limited rows is constructed, which has the properties that for each row of the drive bit matrix, a compatible row exists or can be generated by XOR operation of multiple rows in the dictionary bit matrix and the total number of rows used to compute all compatible rows is minimal. The rows in the dictionary matrix are encoded to further reduce the number of ATE channels and test data volume. Experimental results for the large ISCAS 89 benchmarks show that the proposed method significantly reduces test data volume for multi-scan designs.
2007年S1期 89-94页 [查看摘要][在线阅读][下载 430K] [下载次数：36 ] |[网刊下载次数：0 ] |[引用频次：1 ] |[阅读次数：0 ] - 阚保强;蔡理;徐勇军;
Low-power design is one of the most important issues in wireless sensor networks (WSNs) , while reliable information transmitting should be ensured as well. Transmitting power (TP) control is a simple method to make the power consumption down, but excessive interferences from potential adjacent operating links and communication reliability between nodes should be considered. In this paper, a reliable and energy efficient protocol is presented, which adopts adaptive rate control based on an optimal TP. A mathematical model considering average interference and network connectivity was used to predict the optimal TP. Then for the optimal TP, active nodes adaptively chose the data rate with the change of bit-error-rate(BER) performance. The efficiency of the new strategy was validated by mathematical analysis and simulations. Compared with 802.11 DCF which uses maximum unified TP and BASIC protocol, it is shown that the higher average throughput can achieve while the energy consumption per useful bit can be reduced according to the results.
2007年S1期 95-100页 [查看摘要][在线阅读][下载 500K] [下载次数：58 ] |[网刊下载次数：0 ] |[引用频次：0 ] |[阅读次数：0 ] - 朱彦卿;何怡刚;方葛丰;阳辉;齐绍忠;刘惠;
A novel method based on the analysis of instantaneous phase is proposed to extract the jitter on phase-locked loops output clock. The method utilizes the Hilbert transform to extend the real signal of PLLs output into an analytic signal, and the implementation of Hilbert transform is based on the Fourier transform windowed with Hamming window. Then, the jitter of clock is extracted from the instantaneous phase of analytic signal. The experimental results of simulations validate that the proposed method can effectively extract the jitter on PLL clock, and it has better performance by comparing the sinusoidal jitter extraction results with the other methods.
2007年S1期 101-104页 [查看摘要][在线阅读][下载 392K] [下载次数：68 ] |[网刊下载次数：0 ] |[引用频次：1 ] |[阅读次数：0 ] - 郑淑霞;周书明;
The growing size of the multiprocessor systems increases their vulnerability to component failures. It is crucial to local and to replace the fault processors to maintain system's high reliability. The fault diagnosis is the process of identifying faulty processors in a system through testing. This paper establishes the diagnosabilities of the incomplete star graph Sn (n≥4) with missing links under the PMC model and its variant, the BGM model, and shows that the diagnosabilities of incomplete star graph Sn under these two diagnostic models can be determined by the minimum degree of its topology structure. This method can also be applied to the other existing multiprocessor systems.
2007年S1期 105-109页 [查看摘要][在线阅读][下载 376K] [下载次数：54 ] |[网刊下载次数：0 ] |[引用频次：10 ] |[阅读次数：0 ] - 门朝光;曹刘娟;王立闻;徐振朋;
When applied to mobile computing systems,checkpoint protocols for distributed computing systems would face many new challenges, such as low wireless bandwidth, frequent disconnections, and lack of stable storage at mobile hosts. This paper proposes a novel checkpoint protocol to effectively reduce the coordinating overhead. By using a communication vector, only a few processes participate in the checkpointing event. During checkpointing, the scheme can save the time used to trace the dependency tree by sending checkpoint requests to dependent processes at once. In addition, processes are non- blocking in this scheme, since the inconsistency is resolved by the piggyback technique. Hence the unnecessary and orphan messages can be avoided. Compared with the traditional coordinated checkpoint approach, the proposed non-blocking algorithm obtains a minimal number of processes to take checkpoints. It also reduces the checkpoint latency, which brings less overhead to mobile host with limited resources.
2007年S1期 110-115页 [查看摘要][在线阅读][下载 371K] [下载次数：78 ] |[网刊下载次数：0 ] |[引用频次：2 ] |[阅读次数：0 ] - 王帅;吉吟东;董炜;杨士元;
This paper presents a fault-tolerant computer system. It is designed as a double 2-out-of-2 architecture based on component redundant technique. Also, a quantitative probabilistic model is presented for evaluating the reliability, availability, maintainability and safety (RAMS) of this architecture. Hierarchical modeling method and Markov modeling method are used in RAMS analysis to evaluate the system characteristics. The double 2-out-of-2 system is compared with the other two systems, all voting triple modular redundancy (AVTMR) system and dual-duplex system. According to the result, the double 2-out-of-2 system has the highest dependability. Especially, the system can satisfy the safety integrity level (SIL) 4, which means the system's probability of catastrophic failure less than or equal to 10-8 per hour, therefore, it can be applied to life critical systems such as high-speed railway systems.
2007年S1期 116-121页 [查看摘要][在线阅读][下载 396K] [下载次数：160 ] |[网刊下载次数：0 ] |[引用频次：27 ] |[阅读次数：0 ] - 莫毓昌;刘宏伟;杨孝宗;
Fault tolerant multiple phased systems (FTMPS), i.e., systems whose critical components are independently replicated and whose operational life can be partitioned in a set of disjoint periods, are called "phases". Because of their deployment in critical applications, their reliability analysis is a task of primary relevance to validate the designs. Fault tree analysis based on binary decision diagram (BDD) is one of the most commonly used techniques for FTMPS reliability analysis. To utilize the technique the fault tree structure of FTMPS needs to be converted into the corresponding BDD format. Our research work shows that the system BDD generation algorithms presented in the literature are too inefficient to be used for industrial complex FTPMS because of the problems, such as variable ordering and combination of large BDDs. This paper presents a more efficient approach consisting of a flatting pre-processing technique, a proved efficient ordering heuristic and a bottom-up generation algorithm. The approach tries to combine share-variable BDDs by complex combination operation firstly and then combine no-share-variable BDDs using simple combination operation, thus to alvoid the intensive computations caused by large BDD combination operations. An example FTMPS is analyzed to illustrate the advantages of our approach.
2007年S1期 122-127页 [查看摘要][在线阅读][下载 365K] [下载次数：195 ] |[网刊下载次数：0 ] |[引用频次：18 ] |[阅读次数：0 ] - 余菲;李崇仁;张靖恺;
Phase-locked loops (PLLs) are essential wherever a local event is synchronized with a periodic external event. They are utilized as on-chip clock frequency generators to synthesize a low skew and higher internal frequency clock from an external lower frequency signal and its characterization and measurement have recently been calling for more and more attention. In this paper, a built-in on-chip circuit for measuring jitter of PLL based on a duty cycle modulation vernier delay line is proposed and demonstrated. The circuit employs two delay lines to measure the timing difference and transform the difference signal into digital words. The vernier lines are composed of delay cells whose duty cycle can be adjusted by a feedback voltage. It enables the circuit to have a self calibration capability which eliminates the mismatch problem caused by the process variation.
2007年S1期 128-133页 [查看摘要][在线阅读][下载 396K] [下载次数：64 ] |[网刊下载次数：0 ] |[引用频次：1 ] |[阅读次数：0 ] - 成本茂;王红;杨士元;牛道恒;靳洋;
Scheduling is an important step in high-level synthesis and can greatly influence the testability of the synthesized circuits. This paper presents an efficient testability-improved data path scheduling scheme based on mobility scheduling, in which the scheduling begins from the operation with least mobility. In our data path scheduling scheme, the lifetimes of the I/O variables are made as short as possible to enlarge the possibility of the intermediate variables being allocated to the I/O registers. In this way, the controllability/observability of the intermediate variables can be improved. Combined with a weighted graph-based register allocation method, this scheme can obtain better testability. Experimental results on some benchmarks and example circuits show that the proposed scheme can get higher fault coverage compared with other scheduling schemes at little area overhead and even less time delay.
2007年S1期 134-138页 [查看摘要][在线阅读][下载 375K] [下载次数：46 ] |[网刊下载次数：0 ] |[引用频次：3 ] |[阅读次数：0 ] - 徐拾义;
Although mutation testing is one of the practical ways of enhancing test effectiveness in software testing, it could be sometimes infeasible in practical work for a large scale software so that the mutation testing becomes time-consuming and even in prohibited time. Therefore, the number of faults assumed to exist in the software under test should be reduced so as to be able to confine the time complexity of test within a reasonable period of time. This paper utilizes the concept of fault dominance and equivalence, which has long been employed in hardware testing, for revealing a novel way of reducing the number of faults assumed to hide in software systems. Once the number of faults assumed in software is decreased sharply, the effectiveness of mutation testing will be greatly enhanced and become a feasible way of software testing. Examples and experimental results are presented to illustrate the effectiveness and the helpfulness of the technology proposed in the paper.
2007年S1期 139-145页 [查看摘要][在线阅读][下载 446K] [下载次数：66 ] |[网刊下载次数：0 ] |[引用频次：2 ] |[阅读次数：0 ] - 李光顺;吴俊华;马光胜;
Network on chip (NoC) architectures have been proposed to resolve complex on-chip communication problems. An NoC-based mapping algorithm is shown in this paper. It can map irregular intellectual properties (IPs) cores onto regular tile 2-D mesh NoC architectures. The basic idea is to decompose a large IP into several dummy IPs or integrate several small IPs into one dummy IP, such that each dummy IP can fit into a single tile. It can also allocate buffer space according to the input/output degree and avoid connection congestion by adapting communication density. Experimental data indicate that using the algorithm proposed in this paper, the communication energy can be reduced about 7%.
2007年S1期 146-149页 [查看摘要][在线阅读][下载 386K] [下载次数：121 ] |[网刊下载次数：0 ] |[引用频次：2 ] |[阅读次数：0 ] - 郭涑炜;赵瑞莲;李立健;
The program slicing technique is employed to calculate the current values of the variables at some interest points in software test data generation. This paper introduces the concept of statement domination to represent the multiple nests, and presents a dynamic program slice algorithm based on forward analysis to generate dynamic slices. In the approach, more attention is given to the statement itself or its domination node, so computing program slices is more easy and accurate, especially for those programs with multiple nests. In addition, a case study is discussed to illustrate our algorithm. Experimental results show that the slicing technique can be used in software test data generation to enhance the effectiveness.
2007年S1期 150-155页 [查看摘要][在线阅读][下载 357K] [下载次数：38 ] |[网刊下载次数：0 ] |[引用频次：2 ] |[阅读次数：0 ] - 张雪锋;范九伦;
In order to improve performance and security of image encryption algorithm effectively based on chaotic sequences, an extended chaotic sequence generating method is presented based on logistic chaotic system using Bernstein form Bézier curve generating algorithm. In order to test the pseudorandom performance of the extended chaotic sequence, we also analyze random performance, autocorrelation performance, and balance performance of the extended chaotic sequence. Simulation results show that the extended chaotic sequence generated using our method is pseudorandom and its correlation performance and balance performance are good. As an application, we apply the extended chaotic sequence in image encryption algorithm, the simulation results show that the performance of the encrypted image using our method is better than that using logistic chaotic sequence.
2007年S1期 156-161页 [查看摘要][在线阅读][下载 931K] [下载次数：111 ] |[网刊下载次数：0 ] |[引用频次：18 ] |[阅读次数：0 ] - 尚毅梓;吴保生;李铁键;方神光;
This paper describes a parallel computing platform using the existing facilities for the digital watershed model. In this paper, distributed multi-layered structure is applied to the computer cluster system, and the MPI-2 is adopted as a mature parallel programming standard. An agent is introduced which makes it possible to be multi-level fault-tolerant in software development. The communication protocol based on checkpointing and rollback recovery mechanism can realize the transaction reprocessing. Compared with conventional platform, the new system is able to make better use of the computing resource. Experimental results show the speedup ratio of the platform is almost 4 times as that of the conventional one, which demonstrates the high efficiency and good performance of the new approach.
2007年S1期 162-168页 [查看摘要][在线阅读][下载 507K] [下载次数：124 ] |[网刊下载次数：0 ] |[引用频次：7 ] |[阅读次数：0 ] - 张磊;韩银和;李华伟;李晓维;
As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors' yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors' performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time.
2007年S1期 169-174页 [查看摘要][在线阅读][下载 415K] [下载次数：80 ] |[网刊下载次数：0 ] |[引用频次：16 ] |[阅读次数：0 ] - 赵国生;王慧强;王健;
Stochastic process algebras have been proposed as compositional specification formalisms for performance models. A formal analysis method of survivable network was proposed based on stochastic process algebra, which incorporates formal modeling into performance analysis perfectly, and then various performance parameters of survivable network can be simultaneously obtained after formal modeling. The formal description with process expression to the survivable network system was carried out based on the simply introduced syntax and operational semantics of stochastic process algebra. Then PEPA workbench tool was used to obtain the probability of system's steady state availability and transient state availability. Simulation experiments show the effectiveness and feasibility of the developed method.
2007年S1期 175-179页 [查看摘要][在线阅读][下载 359K] [下载次数：79 ] |[网刊下载次数：0 ] |[引用频次：7 ] |[阅读次数：0 ] - 李光辉;冯冬芹;
ATPG for very large scale integrated circuit designs is an important problem in industry. With the advent of SOC designs, testing and verification of the core-based designs become a challenging problem. This paper presents an algebraic test generation algorithm with unspecified variable assignments. Given a stuck at fault of the circuit with unspecified signals, the proposed algorithm uses a new encoding scheme for unspecified variable assignments, and solves the Boolean satisfiability formula representing the Boolean difference to obtain a test pattern. Experimental results demonstrate the efficiency and feasibility of the proposed algorithm.
2007年S1期 180-185页 [查看摘要][在线阅读][下载 398K] [下载次数：20 ] |[网刊下载次数：0 ] |[引用频次：0 ] |[阅读次数：0 ] - 尚毅梓;靳洋;吴保生;
The distributed system with high performance and stability is commonly adopted in large scale scientific and engineering computing. In this paper, we discuss a fault-tolerant mechanism under Linux circumstance to improve the fault-tolerant ability of the system, namely a scheme and frame to form the stable computing platform. In terms of the structure and function of the distributed system, active list and file invocation strategies are employed in the task management. System multilevel fault-tolerance can be achieved by repeated processes in a single node and task migration on multi-nodes. Manager node agent introduced in this paper administrates the nodes using the list, disposes of the tasks according to the nodes' performance, and hence, to be able to make full use of the cluster resources. An evaluation method is proposed to appraise the performance. The analyzed results show the usefulness of the scheme proposed except for some additional overhead of memory consumption.
2007年S1期 186-191页 [查看摘要][在线阅读][下载 363K] [下载次数：111 ] |[网刊下载次数：0 ] |[引用频次：5 ] |[阅读次数：0 ] - 高建良;徐勇军;李晓维;
In wireless sensor networks (WSNs), a faulty sensor may produce incorrect data and transmit them to the other sensors. This would consume the limited energy and bandwidth of WSNs. Furthermore, the base station may make inappropriate decisions when it receives the incorrect data sent by the faulty sensors. To solve these problems, this paper develops an online distributed algorithm to detect such faults by exploring the weighted majority vote scheme. Considering the spatial correlations in WSNs, a faulty sensor can diagnose itself through utilizing the spatial and time information provided by its neighbor sensors. Simulation results show that even when as many as 30% of the sensors are faulty, over 95% of faults can be correctly detected with our algorithm. These results indicate that the proposed algorithm has excellent performance in detecting fault of sensor measurements in WSNs.
2007年S1期 192-196页 [查看摘要][在线阅读][下载 351K] [下载次数：81 ] |[网刊下载次数：0 ] |[引用频次：12 ] |[阅读次数：0 ] - 白晓平;韦援丰;
Universal serial bus 2.0 (USB2.0) is a kind of mainstream interface technology. The traditional USB developing is only to develop USB peripheral devices. For the USB2.0 peripheral devices IP core system that has wide application foreground, some interference inevitably exists in signal transmitting. Some fault-tolerant design and test methods must be adopted in order to correctly transmit and receive data. Combining with a project, this paper introduces in detail about measures, hardware implement, and test methods of fault-tolerant design about USB2.0 peripheral devices IP core system. Fault-tolerant design measures, noise reduction measures of signal processing, fault-tolerant methods about data encode and decode, package identification (ID) field fault-tolerant methods, and cyclic redundancy checks fault-tolerant methods are discussed. The paper also presents some hardware implement methods about fault-tolerant design of data decode and test methods about fault-tolerant design of USB2.0 IP core system. These methods can offer the reference for development of USB2.0 system in all kinds of electronics instrumentations.
2007年S1期 197-201页 [查看摘要][在线阅读][下载 422K] [下载次数：65 ] |[网刊下载次数：0 ] |[引用频次：3 ] |[阅读次数：0 ] - 郭建立;刘宏伟;董剑;杨孝宗;
Mobile ad hoc networks rely on the cooperation of nodes for routing and forwarding. However, it may not be advantageous for individual nodes to cooperate. In order to make the mobile ad hoc network more robust, we propose a scheme called HEAD (a hybrid mechanism to enforce node cooperation in mobile ad hoc networks) to make the misbehavior unattractive. HEAD is an improvement to OCEAN (observation-based cooperation enforcement in ad hoc networks). It employs only first hand information and works on the top of DSR (dynamic source routing) protocol. By interacting with the DSR, HEAD can detect the misbehavior nodes in the packet forwarding process and isolate them in the route discovery process. In order to detect the misbehavior nodes quickly, HEAD introduces the warning message. In this paper, we also classify the misbehavior nodes into three types:malicious nodes, misleading nodes, and selfish nodes. They all can be detected by HEAD, and isolated from the network.
2007年S1期 202-207页 [查看摘要][在线阅读][下载 323K] [下载次数：72 ] |[网刊下载次数：0 ] |[引用频次：2 ] |[阅读次数：0 ] - 李纪敏;尚朝轩;邹明虎;
The selection of weighting matrix in design of the linear quadratic optimal controller is an important topic in the control theory. In this paper, an approach based on genetic algorithm is presented for selecting the weighting matrix for the optimal controller. Genetic algorithm is adaptive heuristic search algorithm premised on the evolutionary ideas of natural selection and genetic. In this algorithm, the fitness function is used to evaluate individuals and reproductive success varies with fitness. In the design of the linear quadratic optimal controller, the fitness function has relation to the anticipated step response of the system. Not only can the controller designed by this approach meet the demand of the performance indexes of linear quadratic controller, but also satisfy the anticipated step response of close-loop system. The method possesses a higher calculating efficiency and provides technical support for the optimal controller in engineering application. The simulation of a three-order single-input single-output (SISO) system has demonstrated the feasibility and validity of the approach.
2007年S1期 208-211页 [查看摘要][在线阅读][下载 327K] [下载次数：44 ] |[网刊下载次数：0 ] |[引用频次：4 ] |[阅读次数：0 ] - 施银盾;徐拾义;
This paper develops an improved structural software complexity metrics named information flow complexity which is closely related to the reliability of software. Together with the three software complexity metrics, the total software complexity is measured and some rules to reduce the complexity are presented in the paper. To illustrate and explain the process of measurement and reduction of software complexity, several examples and experiments are given. It is proposed that software complexity metrics can be measured earlier in software development and can provide substantial information of software systems whose reliabil- ity can be modeled and used in the determination of initial parameter estimation.
2007年S1期 212-216页 [查看摘要][在线阅读][下载 327K] [下载次数：50 ] |[网刊下载次数：0 ] |[引用频次：2 ] |[阅读次数：0 ] - 王健;王慧强;赵国生;
This paper describes a novel quantitative analysis model for system survivability based on conflict analysis, which provides a direct-viewing survivable situation. Based on the three-dimensional state space of conflict, each player's efficiency matrix on its credible motion set can be obtained. The player whose desire is the strongest in all initiates the moving and the overall state transition matrix of information system may be achieved. In addition, the process of modeling and stability analysis of conflict can be converted into a Markov analysis process, thus the obtained results with occurring probability of each feasible situation will help the players to quantitatively judge the probability of their pursuing situations in conflict. Compared with the existing methods which are limited to post-explanation of system's survivable situation, the proposed model is relatively suitable for quantitatively analyzing and forecasting the future development situation of system survivability. The experimental results show that the model may be effectively applied to quantitative analysis for survivability. Moreover, there will be a good application prospect in practice.
2007年S1期 217-222页 [查看摘要][在线阅读][下载 359K] [下载次数：67 ] |[网刊下载次数：0 ] |[引用频次：1 ] |[阅读次数：0 ] - 李天;王之梁;尹霞;
The session initiation protocol (SIP) is a signaling protocol for Internet telephony, multimedia conferencing, presence, event notification, and instant messaging. With the gaining popularity, more and more SIP implementations have been developed and deployed. How to guarantee the conformance of those SIP implementations is the key point of interconnection and interoperation among them. This paper proposes the test method and architecture for the SIP protocol based on the IPv6 tester system. Tree and tabular combined notation (TTCN-2) is adopted to describe the test suite. With an enhanced reference implementation, the data-processing ability to the original test system has been greatly improved. In the following test practices, some errors have been found in the SIP entities under test. It is proved that the proposed test method and architecture are effective to verify the conformance of the SIP entities, and the result of the conformance test may provide helpful reference to the development of SIP products.
2007年S1期 223-228页 [查看摘要][在线阅读][下载 388K] [下载次数：53 ] |[网刊下载次数：0 ] |[引用频次：1 ] |[阅读次数：0 ] - 郭杰荣;何怡刚;刘美容;唐圣学;李宏民;
Errors of mismatch and currents calibration caused by channel geometrical variety in switchedcurrent are investigated in this paper. The relation and computing of mismatch and sensitivity are discussed also, and then a measure method of switched current mismatch using wavelet decomposition is proposed. A selected group of same transconductance is choosing as a cohort firstly, and the sensitivities of cohort in relation to the variation of transconductance are computed. Compared with the nominal deviation and tolerance borderline, the optimization and testing can be performed. As an example, a sixth order chebyshev low-pass filter is simulated and tested. The results have justified the reliability and feasibility of the method.
2007年S1期 229-234页 [查看摘要][在线阅读][下载 386K] [下载次数：37 ] |[网刊下载次数：0 ] |[引用频次：1 ] |[阅读次数：0 ] - 翁延玲;葛海通;严晓浪;任坤;
An information extraction-based technique is proposed for RTL-to-gate equivalence checking. Distances are calculated on directed acyclic graph (AIG). Multiplier and multiplicand are distinguished on multiplications with different coding methods, with which the operand ordering/grouping information could be extracted from a given implementation gate netlist, helping the RTL synthesis engine generate a gate netlist with great similarity. This technique has been implemented in an internal equivalence checking tool, ZD_VIS. Compared with the simple equivalence checking, the speed is accelerated by at least 40% in its application to a class of arithmetic designs, addition and multiplication trees. The method can be easily incorporated into existing RTL-to-gate equivalence checking frameworks, increasing the robustness of equivalence checking for arithmetic circuits.
2007年S1期 235-239页 [查看摘要][在线阅读][下载 366K] [下载次数：26 ] |[网刊下载次数：0 ] |[引用频次：3 ] |[阅读次数：0 ] - 程宇新;张磊;依那;项海格;
Bit-interleaved coded modulation (BICM) is suitable to bandwidth-efficient communication systems. Hybrid automatic repeat request (HARQ) can provide more reliability to high-speed wireless data transmission. A new path weight complementary convolutional (PWCC) code used in the type-Ⅱ BICM-HARQ system is proposed. The PWCC code is composed of the original code and the complimentary code. The path in trellis with large hamming weight of the complimentary code is designed to compensate for the path in trellis with small hamming weight of the original code. Hence, both of the original code and the complimentary code can achieve the performance of the good code criterion of corresponding code rate. The throughput efficiency of the BICM-HARQ system wit PWCC code is higher than repeat code system, a little higher than puncture code system in low signal-to-noise ratio (SNR) values and much higher than puncture code system, the same as repeat code system in high SNR values. These results are confirmed by the simulation.
2007年S1期 240-245页 [查看摘要][在线阅读][下载 349K] [下载次数：54 ] |[网刊下载次数：0 ] |[引用频次：1 ] |[阅读次数：0 ] - 蒿敬波;殷建平;张波云;
The fault tolerance of scale-free networks is examined in this paper. Through the simulation on the changes of the average path length and network fragmentation of the Barabasi-Albert model when faults happen, it can be observed that generic scale-free networks are quite robust to random failures, but are very vulnerable to targeted attacks at the same time. Therefore, an existing optimization strategy for the robustness of scale-free networks to failures and attacks is also introduced. The simulation similar with the above proved that the so-called (1,0) network has potentially interconnectedness closer to that of a scale-free network and robustness to targeted attacks closer to that of an exponential network. Furthermore,its resistance to random failures is better than that of either of them.
2007年S1期 246-249页 [查看摘要][在线阅读][下载 393K] [下载次数：38 ] |[网刊下载次数：0 ] |[引用频次：1 ] |[阅读次数：0 ] - 丁志刚;汪泓澄;凌良合;
This paper introduces strategies to detect software bugs in earlier life cycle stage in order to improve test efficiency. Static analysis tool is one of the effective methods to reveal software bugs during software development. Three popular static analysis tools are introduced, two of which, PolySpace and Splint, are compared with each other by analyzing a set of test cases generatedd by the authors. PolySpace can reveal 60% bugs with 100% R/W ratio (ratio of real bugs and total warnings), while Splint reveal 73.3% bugs with 44% R/W ratio. And they are good at finding different categories of bugs. Two strategies are concluded to improve test efficiency, under the guideline that static analysis tools should be used in finding different categories of bugs according to their features. The first one aims at finding bugs as many as possible, while the second concentrates to reduce the average time on bug revelation. Experimental data shows the first strategy can find 100% bugs with 60% R/W ratio, the second one find 80% bugs with 66.7% R/W ratio. Experiment results prove that these two strategies can improve the test efficiency in both fault coverage and testing time.
2007年S1期 250-254页 [查看摘要][在线阅读][下载 426K] [下载次数：48 ] |[网刊下载次数：0 ] |[引用频次：3 ] |[阅读次数：0 ] - 张应辉;饶云波;周明天;
Crew rostering system is a daily grind in the management of both corporation and enterprise. A fair and reasonable rostering method plays a very important role in the arousing worker's enthusiasm and improving the work efficiency. This paper presents a method of building models for automatic crew rostering mode with computer and advancing the multi-objective optimum scheme. The method to build models for crew rostering system is also discussed. The question to crew rostering system model is solved by genetic algorithms and simulated annealing algorithms. Simulation results show the correctness of algorithms. The actual data of the airways have justified its reasonability and efficiency.
2007年S1期 255-259页 [查看摘要][在线阅读][下载 333K] [下载次数：61 ] |[网刊下载次数：0 ] |[引用频次：4 ] |[阅读次数：0 ] - 谭阳红;何怡刚;方葛丰;
A novel hierarchical neural networks (HNNs) method for fault diagnosis of large-scale circuits is proposed. The presented techniques using neural networks(NNs) approaches require a large amount of computation for simulating various faulty component possibilities. For large scale circuits, the number of possible faults, and hence the simulations, grow rapidly and become tedious and sometimes even impractical. Some NNs are distributed to the torn sub-blocks according to the proposed torn principles of large scale circuits. And the NNs are trained in batches by different patterns in the light of the presented rules of various patterns when the DC, AC and transient responses of the circuit are available. The method is characterized by decreasing the over-lapped feasible domains of responses of circuits with tolerance and leads to better performance and higher correct classification. The methodology is illustrated by means of diagnosis examples.
2007年S1期 260-265页 [查看摘要][在线阅读][下载 438K] [下载次数：46 ] |[网刊下载次数：0 ] |[引用频次：4 ] |[阅读次数：0 ] - 褚彦明;徐拾义;
Traditionally, timing and the failure rate are the only two factors considered in software reliability formula, which is actually incomplete. Reliability should be redefined as a function of software complexity, test effectiveness, and operating environment. This paper focuses on software complexity with its relation to the soft- ware reliability. Today, many software complexity measurements have been proposed, but most of them treat the reliability model incompletely. This paper proposes a new method which considers a relatively complete view of software reliability including its complexity and test effectiveness of the software being tested.
2007年S1期 266-269页 [查看摘要][在线阅读][下载 372K] [下载次数：48 ] |[网刊下载次数：0 ] |[引用频次：2 ] |[阅读次数：0 ] - 蔡金燕;韩春辉;孟亚峰;
In every field of engineering, testing is a fundamental step for the validation of design, being the most direct way to verify that a product meets its specifications. If the desired performance is not achieved, testing should identify all the causes of malfunctioning and indicate suitable corrective actions. Different algorithms relying on the symbolic approach have been presented in the past by the authors and in this work noteworthy improvements on these algorithms are proposed. However, how the testability is designed to maintain devices during its lifetime is discussed lack at present. Furthermore, this problem concerns needing more times on testing and fault diagnosis, and wasting more manpower and material resources. Especially in the army devices field, it is very important that maintenance and indemnificatory are advanced. In this paper, the parameters in testability design for fault detection and diagnosis will be given. The detailed contents of testability will be proposed, including the dividing of circuit module in equipment, technology material needed for detection and requirement of specifications used for testing.
2007年S1期 270-274页 [查看摘要][在线阅读][下载 346K] [下载次数：50 ] |[网刊下载次数：0 ] |[引用频次：2 ] |[阅读次数：0 ] 下载本期数据